In general, operational amplifiers are versatile integrated circuits that are commonly implemented in various types of electronic circuits. For instance, operational amplifiers are typically used as output drivers for LCD (liquid crystal display) devices, DACs (digital-to-analog converters), ADCs (analog-to-digital converters), switched capacitor filters, analog filters, etc. In LCD devices, source driver circuits are constructed using operational amplifiers as source line drivers for driving an output signal to transfer an amplified color signal to a TFT LCD panel. The source line drivers operate by differentially amplifying input signals applied to non-inverting and inverting input terminals of a differential input stage of the operational amplifiers.
With operational amplifiers, the performance and reliability of the electronic circuit depends on the slew rate, or the response speed of an output signal as function of an input signal. Currently, high resolution LCD panel displays such as QVGA (quarter video graphic array) and VGA (video Graphics Array) are continually being developed and optimized to provide increasing resolution. As the resolution increases, the activation period of the input signal to drive the TFT-LCD panel becomes shorter. As a result, it is important that the slew rate of the differential amplifier be minimized.
FIG. 1 illustrates a conventional operational amplifier (100) having a two-stage topology that provides rail-to-rail common mode range of operation at the input and output of the operational amplifier. In general, the operational amplifier (100) comprises a differential input circuit (110), a folded cascode stage (120) (gain stage) and a class AB output stage (130). The differential input circuit (110) and folded cascode stage (120) form a folded cascode OTA (operational transconductance amplifier) amplifier which amplifies the difference of two input voltages applied to a non-inverting INP and inverting INN terminals, and generates a current at the output stage (130). In addition, the operational amplifier (100) comprises a frequency compensation circuit (140) that implements a known cascoded Miller frequency compensation scheme to enhance phase margin and reduce oscillation, as is known in the art. The architecture and operation of the operational amplifier (100) is well-known in the art, and a detailed explanation is not necessary. For illustrative purposes, however, a brief description of constituent components and functions of the operational amplifier (100) will be provided hereafter.
The differential input circuit (110) is designed to provide rail-to-rail operation, wherein an input common mode voltage can vary throughout the range between the positive power supply rail voltage VDD and the negative power supply rail voltage VSS. The differential input circuit (110) comprises a first differential amplifier comprising PMOS transistors DTR11 and DTR12, a second differential amplifier comprising NMOS transistors DTR21 and DTR22, a first current source ITR1 and a second current source ITR2. The PMOS transistors DTR11 and DTR12 (of the first differential amplifier) are a matched transistor pair having a common source configuration with source electrodes commonly connected to a node N10. The first current source ITR1 is connected between the node N10 and a positive supply rail voltage VDD. The first current source ITR1 is a PMOS transistor, which sinks a bias current IB1 of the first differential amplifier so that substantially constant bias current is provided to the PMOS transistors DTR11 and DTR12. A bias control voltage VB1 input to a gate electrode of the PMOS transistor ITR1 controls the quantity of the bias current IB1 provided to the first differential amplifier.
Likewise, the NMOS transistors DTR21 and DTR22 (of the second differential amplifier) are a matched transistor pair having a common source configuration with source electrodes commonly connected to a node N20. The second current source ITR2 is connected between the common node N20 and a negative supply rail voltage VSS. The second current source ITR2 is an NMOS transistor, which sinks a bias current IB2 of the second differential amplifier so that substantially constant bias current is provided to the NMOS transistors DTR21 and DTR22. A bias control voltage VB6 input to a gate electrode of the transistor ITR2 controls the quantity of the bias current IB2 provided to the second differential amplifier. Typically, the bias control voltages VB1 and VB6 are controlled such that the bias current IB1 provided to the first differential amplifier is substantially the same value as the bias current IB2 provided to the second differential amplifier (i.e., IB1=IB2).
The gate electrodes of the transistors DTR11 and DTR21 are commonly connected to a positive (non-inverting) input terminal INP, and the gate electrodes of the transistors DTR12 and DTR22 are commonly connected to a negative (inverting) input terminal INN. The drain electrodes of the NMOS transistors DTR21 and DTR22 are output terminals connected to nodes N1 and N1′ in the folded cascode stage (120). The drain electrodes of the PMOS transistors DTR11 and DTR12 are output terminals connected to nodes N2 and N2′ in the folded cascode stage (120).
In general, the folded cascode stage (120) comprises a summing circuit formed of two current mirrors and a common floating current source that drives the current mirrors. In particular, the folded cascode stage (12) comprises a first set of control transistors comprising PMOS transistors CTR1, CTR2, CTR3 and CTR4 and a second set of control transistors comprising NMOS transistors CTR5, CTR6, CTR7 and CTR8. The first set of control transistors CTR1˜CTR4 form a first current mirror and the second set of control transistors CTR5˜CTR8 form a second current mirror. Further, bias transistors BTR1 and BTR3 form the floating current source which drives the current mirrors. An external bias voltage VB2 is applied to the gates of CTR3 and CTR4, and an external bias voltage VB5 is applied to the gates of CTR5 and CTR6. Further, external bias voltages VB3 and VB4 are applied to the gates of BTR1 and BTR3, respectively.
The summing circuit operates to add the output currents of the differential amplifiers in the differential input stage (110) so as to provide drive currents for the driver output stage (130). In particular, the first current mirror CTR1˜CTR4 is loaded by the drain currents of the input pairs DTR21 and DTR22 and the second current mirror CTR5˜CTR8 is loaded by the drain currents of the input pair DTR11 and DTR12. The current mirror circuits operate to mirror the output currents at nodes N1′ and N2′ and add these currents to the currents at nodes N1 and N2 to provide drive currents for the output stage (130).
The output stage (130) comprises a class-AB rail-to-rail output stage comprising a pair of common source connected output transistors PUTR and PDTR, which are connected to control nodes NC1 and NC2, respectively. The cascode stage (120) includes a bias control circuit formed by a complementary pair of transistors BTR2 and BTR4 to provide class AB control. The transistors BTR2 and BTR4 are connected in parallel between control nodes NC1 and NC2 to supply drive currents in parallel to the output transistors PUTR and PDTR, and are biased with bias voltage VB3 and VB4, respectively. The class-AB action is performed by maintaining the voltage between the gates of the output transistors PUTR and PDTR constant (i.e., NC1−NC2=constant). The floating current source biases the summing circuit as well as the class AB control circuit. The bias control transistors BTR2 and BTR4 and similar in structure to the floating current source transistors BTR1 and BTR3, which results in a quiescent current that is independent of the supply voltage.
The frequency compensation circuit (140) includes compensation capacitors C1 and C2, which are connected between the output node NOUT and the cascode stage (120) to provide cascoded Miller compensation, as is known in the art. The first capacitor C1 is connected between the output node NOUT and node N1 and the second capacitor C2 is connected between the output node NOUT and node N2. In general, the compensation circuit (140) operates to provide necessary compensation to maintain the stability when the operational amplifier is configured with feedback and increase the phase margin. However, the addition of the compensation capacitors introduces slewing of the output signal as a result of the time delay for charging and discharging the capacitors when driving the output node NOUT.
More specifically, in the conventional amplifier of FIG. 1, the slew rate of the output signal is predominately determined by the current IS that is available to charge and discharge the compensation capacitors C1 and C2. The slew rate of the output signal is determined as
      SR    =                            ⅆ          Vo                          ⅆ          t                    =              IS                  C          ⁢                                          ⁢          1                      ,where Vo is the output voltage, where the available current IS for slewing is the bias current of the differential amplifier (IB1=IB2), and where C1=C2 is the capacitance of compensation capacitors. When designing the amplifier (100), the capacitors C1 and C2 are typically first selected using known techniques based on, e.g., amplifier gain, the frequency of operation, the load impedance, desired settling time, etc., to achieve the desired stability. The slew rate will then be determined by the bias current IB1=IB2 of the differential amplifier. For example, in conventional TFT-LCD source driver circuits that implement the differential amplifier of FIG. 1, for example, the bias current IB1=IB2 is selected so as to satisfy a maximum driver output setup time, tD, which is required when output voltage Vout swings at a maximum value.
FIG. 4 is an exemplary waveform diagram that illustrates input and output voltages of the operational amplifier (100) when configured as a single-ended, non-inverting differential amplifier with unity gain (i.e., the output node NOUT is connected to the inverting input INN of the differential amplifiers. Ideally, the output voltage waveform (denoted as PD) should track the input voltage waveform (denoted as INP). However, the rising and falling edges of the output voltage PD have sloped transitions where the slope is determined by the slew rate. In FIG. 1, the slewing of the output signal NP is due to the time required for charging/discharging the compensation capacitors C1, C2 when the output voltage at node NOUT changes from Vo1 to Vo2. In such instance, the voltage across the compensation capacitors C1, C2 must be changed by ΔV=Vo1−Vo2, which requires the capacitors C1, C2 to be charged/discharged by CΔV. The nodes of the compensation capacitors C1, C2 connected to the output node NOUT can be readily charged or discharged by the output currents that flow through PUTR and PDTR. However, the nodes of the compensation capacitors C1, C2 connected to cascode node N1 and N2 are charged/discharged by a small current IS, which has a maximum value equal to bias currents IB1=IB2, which effectively limits the slew rate.
To improve the slew rate, either the size of the compensation capacitors C1 and C2 must be decreased or the bias current of the differential amplifiers must be increased. Reducing the size of compensation capacitors C1 and C2, however, results in decreased stability and oscillation of the output voltage, which is undesirable. Although the bias currents can be increased to improve the slew rate, this is undesirable as increased bias current levels result in increased power dissipation.